This invention relates generally to framing or frame synchronizing devices for use in digital transmission systems and more particularly to circuit means used in such devices for frame holding (or forward protection of frame synchronization).
Conventionally, frame synchronizing devices include a comparison circuit for comparing input data with local framing signal bit-by-bit, a framing detector (or frame protecting circuit) operable on the output of the comparison circuit to detect the framing status, and hunting (or searching) means operable under the control of the detector output signal to time-shift the local framing signal so that correct framing is achieved. With such devices, a framing error signal pulse is produced when pulses detected in the comparison circuit are not in coincidence, but such error signal pulse may also result from a spurious out-of-frame condition such as caused temporarily by external disturbance possibly added to the input data. Therefore, framing devices are often designed so as not to decide that framing is lost immediately upon detection of any such temporary out-of-frame condition as resulting from external disturbance, but to decide that framing is lost and start reframing only if and when a framing error signal pulse has been repeated for a predetermined length of time. The length of time during which framing error pulses are ignored is referred to as "forward protecting time". Subsequently, when the detector is in the "framing status", one an out-of-frame condition is detected, the detector remains in the framing status for a definite length of time following the start of reframing even when framing error pulses are no longer produced. The purpose of the latter is for safety in operation. This length of time is referred to as "backward protecting time". The circuit arrangement used to determine the magnitude of the forward and backward protecting time typically takes the form of a counter circuit and is comprised in the framing detector circuit. Namely, framing error pulses from the comparison circuit are counted in the framing detector circuit, for example, up to l bits. The full count number of bits, l, represents the forward protecting time of the device. The output of the framing detector or counter circuit is fed to the hunting means as a control signal therefor whereby reframing is started. Any desired length of forward protecting or frame holding time can thus be obtained by selecting an appropriate counter size or full number of bits to be counted in the framing detector circuit.
In order to increase the length of forward protecting time, however, it is necessary to widely increase the number of counter stages or to substantially enhance the hysteresis characteristics of the integrator circuit and the circuit arrangement must inevitably be complicated, including an increased number of component parts.
On the other hand, any exceptional increase in size of the counter circuit provided to count framing error pulses makes it difficult to restore the framing status once reframed erroneously in the reframing process and, in the worst case, detection of out-of-frame conditions is made impossible as the coincidence (YES) counter reaches full count before the out-of-coincidence (NO) counter reaches full count. To cope with this situation, resort may be had, for example, to use of a coincidence counter having a sufficient number of stages but this unavoidably results in an extended backward protecting time.